[LiangChiu]

Dear Sirs:

Since CA7 is in-order pipeline and there is no instructions ordering problem in CA7, Do we still need DMB on in-order pipeline such as CA7 processor?
For device memory, I think we should map non-cached and for cache maintenance we should use DSB. In which case the DMB should be used on in-order pipeline series?


Regards
Liang

[isogen74]

Let's start with "yes" - it will make your code portable to other processors without change. There are a few other good reasons too (DMB has other side effects such as ensuring some CP15 ops are comitted before the next instruction proceeds, draining the write buffer, etc.). Skipping DMB's / DSB's is a micro-optimization which you will regret later when you run code on a different core (by which point you will have forgotten you omitted them and you have to chase hard to debug errors)...

[LiangChiu]

Dear Isogen74:

Thanks for your reply in detail. Help us to clarify our thinking.

Regards
Liang