[quy]

Hi there,
I am wondering about the relationship between rready and rvalid signals (or wready and wvalid signals). when I do a burst write operation (or burst read) with burst length of 4 transfers, I mean that the wvalid (or rvalid) signals must be asserted in at least 4 clock cycles from when write data (or read data) is available on the data bus, but I don't sure about whether wready (or rready) signal must be asserted at least 4 clock cycles (based burst length) or not to make the transmission of 4 transfers in burst operation. Can you help me for explaining it?
Many thanks.

[maheshp]

Hi Quy,
For any read or write burst, the wvalid or rvalid has to be high for every valid transfer in a burst... the wlast will only be high for the last transfer in the burst....
Regards
mahesh

[ttfn]

AXI has five channels (AW, W, B, AR and R) each has a xVALID and x READY.

xVALID says that there is currently "valid" data on the channel to be sample.

xREADY means the receiver is ready to receive data.

Therefore a transfer occurs on that channel when xREADY and xVALID are asserted at the same time.

For example....
The master puts some data on the WDATA signal, it then asserts WVALID so that the slave knows there is data there. The slave asserts WREADY when it is ready receive the data. Now if the slave is slow, WVALID could be asserted for a number of cycles before the slave asserts WREADY.

I'm not sure where you got the four cycles from. For a transfer to take place both signals must be assert during the same cycle. If you have four things to transfer (e.g. four beats of a burst) then this would have to happen four times. There might not be a gap between transfers, in which case you'd just see the signals asserted for four cycles.

[quy]

Hi maheshp and ttfn,
Thanks for your explanations. Base them, I understood the dependency of READY and VALID signals clearly.