Hi,
I have a question about HWDATA in address phase of the master write access.
In AMBA® 3 AHB-Lite Protocol v1.0 Specification, figure 3-5 "Multiple transfers" , shows the consecutive AHB-Lite master access diagram.
T3-T4 is the address phase of write© access. At this time HWDATA value is not defined.
Is it OK to set any value for example "32'bxxxx_xxxx" during T3-T4 ? Or HWDATA must keep T2-T3 value ?
Please let me know.
Appreciate your help.
Best Regards,
Shingo Kadouchi
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AHB-Lite: HWDATA value in address phase
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JD 
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Posted 25 June 2012 - 01:47 PM
Hi,
From T1 to T2 is the address phase of read access B, so from T2 to T4 is the data phase of this read access.
During this T2-T4 time the HWDATA bus is not being used (as it is a read access), so you would usually either see a default value (perhaps 32'h0000_0000) driven by the master, or else the master would just keep the previous write data valid to avoid unnecessary bus transitions.
You could also simulate using 32'hxxxx_xxxx, but this could cause problems when simulating gate level netlists where X is not always modelled correctly, so I would prefer to avoid using X if possible.
HWDATA is undefined during the read access data phase, so you can in theory use any value you want.
JD
From T1 to T2 is the address phase of read access B, so from T2 to T4 is the data phase of this read access.
During this T2-T4 time the HWDATA bus is not being used (as it is a read access), so you would usually either see a default value (perhaps 32'h0000_0000) driven by the master, or else the master would just keep the previous write data valid to avoid unnecessary bus transitions.
You could also simulate using 32'hxxxx_xxxx, but this could cause problems when simulating gate level netlists where X is not always modelled correctly, so I would prefer to avoid using X if possible.
HWDATA is undefined during the read access data phase, so you can in theory use any value you want.
JD
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