[Ketnawang]

Hello, at the moment i study the LPC11U1x manual(Cortex-M0) and i found some very confusing thing, in the GPIO interrupt registers to enable a rising edge or level interrupt i can set a bit in IENR or delete a bit to disable the interrupt. but the CIENR disables a interrupt by deleting the corresponding bit in IENR and again there is SIENR that only set the corresponding bit in IENR

ISEL Pin Interrupt Mode register: Selects if edge or level sensitive

IENR Pin Interrupt Enable: Enables rising edge/level interrupt
0 = Disable rising edge or level interrupt.
1 = Enable rising edge or level interrupt

SIENR Set Pin Interrupt Enable
0 = No operation.
1 = Enable rising edge or level interrupt.

CIENR Clear Pin Interrupt Enable
0 = No operation.
1 = Disable rising edge or level interrupt.

IST Pin Interrupt Status register
1 = (edge-sensitive): clear rising- and falling-edge detection for this pin.

So if i have a rising edge interrupt i can set him over IENR or SIENR
if i wont to disable the interrupt i can do that by IENR or CIENR or IST
so IST my make sense but why CIENR and SIENR

is this for compatibility with other cortex`s?. did i understood it right?

Regards Thomas

[Joseph Yiu]

Hi Thomas,

I guess you are reading
http://www.nxp.com/d...ual/UM10462.pdf
IENR, SIENR and CIENR are physically one hardware register. The reason for having SIENR and CIENR is to allow a interrupt to be enable/disable using a single access. Otherwise, if using IENR to enable/disable just one interrupt, you need a read-modify-write sequence.
If a interrupt happen between the read and the write, and the interrupt service routine (ISR) modifies another bit in the IENR, the change made by the ISR will be lost after interrupt return because the write back of IENR.

Similarly, IENF, SIENF and CIENF are also one physically register.

I haven't use this chip before, so not entirely sure if my understand is correct.

         		PMODE(ISEL)   ENRL(IENR)  ENAF(IENF)
  
Disable            	X   		0 		X
High level     		0   		1 		1
Low level          	0   		1 		0
Rising edge        	1   		1 		0
Falling edge   		1   		1 		1

If you have setup the design as edge trigger interrupt, you can write 1 to IST register inside your interrupt service routine to clear the interrupt request.

If you have setup the design as level trigger interrupt, you can write 1 to IST register inside your interrupt service routine to toggle the trigger level. By doing this, you can make the interrupt trigger on both rising and falling edges.

Hope it make sense.
regards,
Joseph

This post has been edited by Joseph Yiu: 12 June 2012 - 12:15 PM

[Ketnawang]

It makes sens new for me with the "extra" register, i was wondering but without having to do read modify write sequence, i just write to the register that makes a big different .
so GPIO (SET,CLR) is basically the same thing or ?

p.s.
I got your cortex-m0 book today it relay funny that i get your reply, even before the book was with me ;-) . thank's a lot.

[Joseph Yiu]

Hi Thomas,

Yes, the GPIO SET0/CLR0, SET1/CLR1 are the same. Each GPIO pin can be used by different tasks in the software and this arrangement avoid any conflicts caused by read-modify-write sequences.

Hope you find the book useful. :-)
regards,
Joseph