[MarcoMac]

Hello everyone,
I'm studying the MPU of the Cortex M3 for a university project and I have some questions...

• After I set up a region, where the MPU saves the informations on that region?
• In the MPU Region Attribute and Size Register the bit C (cachable) refers only to an external cache, right? Because CM3 doesn't have a cache.
• In the same register, if TEX=b000 C=1 B=1 we have "Outer and Inner write back. No write allocate". What it means "No write allocate"?
• I found that post on the "Strongly Ordered" memory type. is it correct?

  Quote

  Load/stores to Normal memory may result in any size and number of transactions being presented to the memory system, e.g. a byte load might appear as a word read to the memory, or two neighbouring half-word stores might be merged into a single word write. In addition, near-arbitrary caching and prefetching could be performed.
  Explicit load/stores to Device and Strongly-Ordered regions always produce the exact size and number of transactions, e.g. a single byte load produces a single byte read, two neighbouring half-word stores produce two distinct half-word writes.
  With respect to ordering, accesses to normal memory may be reordered (within certain bounds), e.g. a load from A followed by a load from B in the program may actually be presented as read B, then read A. Accesses to Device and Strongly-Ordered always appear in the order they are listed in the program; so what's the difference between Device and Strongly-Ordered....
  Device accesses are only ordered with respect to other Device accesses, whilst Strongly-Ordered are ordered with respect to *all* other explict load/stores. e.g load-norm-A, load-dev-B, load-dev-C, load-norm-D could be performed as ADBC, or even DBCA; whilst load-norm-A, load-so-B, load-so-C, load-norm-D must be performed as ABCD.
  

I think it's all. if I'll have more questions I'll add them in this topic.

Thank you in advance for your answers,
Marco

ps. sorry for my english

[Joseph Yiu]

1. After I set up a region, where the MPU saves the informations on that region?

In hardware registers inside the MPU.

2. In the MPU Region Attribute and Size Register the bit C (cachable) refers only to an external cache, right? Because CM3 doesn't have a cache.

Yes, correct.

3. In the same register, if TEX=b000 C=1 B=1 we have "Outer and Inner write back. No write allocate". What it means "No write allocate"?

Write allocate : If a cache controller is present, it can allocate a cache line for this data and read the rest of the data in this cache line. So next time a nearby data (in the same cache line) is accessed, the data is already in the cache. Write allocate is usually used with write back cache scheme.

No-write allocate is usually use with write through cache.

4. I found that post on the "Strongly Ordered" memory type. is it correct?

This description is from architecture point of view. However, I think the example at the last section seems incorrect. Ordering of normal data access and device/strongly order memory might not need to be retained (Note: ARMv7-M architecture reference manual revision D is updated to be consistent with ARMv7-A/R in this aspect). Ideally you should read the full text in ARMv7-M architecture reference manual.
However, in Cortex-M3 the design is relatively small and there is no re-ordering of memory accesses.

> so what's the difference between Device and Strongly-Ordered....

1. Device memory can be defined as shareable and non-shareable. Memory re-ordering can take place between shareable and non-shareable devices. Strongly-ordered memory does not allow this.

2. In Cortex-M3, a memory write to device region can often be buffered. It means instruction after the write (if not a memory access instruction) could started before the write is finished. However, the processor should not start any other operation after a strongly order write until the write is completed.

regards,
Joseph