Hiii,
I have one more doubt regarding to AXI
1. If master is asserting the AWVALID and slave is not asserting the AWREADY at all. so for how many clock cycle the AWVALID is asserted high. I thought that till 16 clock cycle it will wait after that error will come .
It is right or not.
If not then tell the answer for that. ITS urgent PLease respond.
Thanks
Sumit
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AXI AWVALID and any AWREADY Time out?
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JD 
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Posted 20 April 2012 - 02:42 PM
Sumit,
This new question probably should have been under a new subject name, otherwise people not interested in "Protection unit support" wouldn't see it.
There is no "time-out" feature for a transaction in the AXI protocol document, once the VALID signal is asserted it must remain asserted until the channel handshake completes. There is no "16 clock cycle" limit, and no error response defined for this scenario.
If your master or slave has a fault, the only way of ending the transaction would be a reset, so catch any issues like this during simulation.
JD
This new question probably should have been under a new subject name, otherwise people not interested in "Protection unit support" wouldn't see it.
There is no "time-out" feature for a transaction in the AXI protocol document, once the VALID signal is asserted it must remain asserted until the channel handshake completes. There is no "16 clock cycle" limit, and no error response defined for this scenario.
If your master or slave has a fault, the only way of ending the transaction would be a reset, so catch any issues like this during simulation.
JD
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