i just want to know how does nesting interrupt work on Cortex M3.
Register PRIMASK, BASEPRI and FAULTMASK are usefull if i want to ignore ,when occurs, certain interrupt (by setting a priority level threshold) ignore= interrup not accepted, interrupt not nested
Register like SETENA enable or disable specific interrupt ( by # )
When the processor is handling an exception and comes an interrupt that has upper priority level, the current exception is nested (save register etc etc ) and the new exception is executed. If the priority of the new interrupt is lower , the NVIC will not nest the interrupt, it will be ignored.
is correct what i've understood? is there something that i miss?
thank you in advance
ps i'm sorry for my bad english
This post has been edited by Nino C: 29 May 2012 - 03:27 PM