[Ravikkamtalwar]

Hi,

I'm using ARM MPCore ACP (Accelerator Coherency Port), which has access to CPU cache. And has low latency when there is cache hit.

When I used this port, it worked properly, functionality wise. But I did not see any performance improvement.
When I was going through the docs, I came to know that we have to enable MMU for D-cache usage and enable SCU.
Still I'm not sure what else have to be enabled to make use of ACP.

My system has no operating system.

Please let me know the steps to be followed for ACP use.

And also let me know, for D-cache, how to set cacheable memory region.

Thanks in advance,

Regards,
Ravi

[ttfn]

You don;t mention which processor you are using (Cortex-A9/5/7/15).

Either way you will need to set up the cores/coherency logic. For an A9 processor this means...
* Enable the MMU on each core, with coherent address regions marked as WB/WA cacheable and Shared
* Enable the L1 data cache on each core
* Set the ACTLR.SMP and ACTLR.FW bits on each core
* Enable the SCU

If you have DS-5, it ships with a baremetal example on how to set this all up.

My experience of the ACP (admittedly limited) is that the main benefit is not having to manually handle coherency in software.

[Ravikkamtalwar]

Thanks for the quick reply.

I'm using Cortex A9 MPCore.

I do not have DS-5. If you can send me the example, that will be a great help.

Regards,
Ravi

[scott]

You can download a DS-5 evaluation from http://www.arm.com/p...5-downloads.php; it includes the examples.

[Ravikkamtalwar]

Thank you