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ARM Community: AHB Wait cycle behavior - ARM Community

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AHB Wait cycle behavior Rate Topic: ****- 1 Votes

#1 User is offline   yakabe 

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Posted 25 April 2012 - 10:28 AM

Hi,

I would like to ask you about AHB-lite wait cycle behavior.
In the AHB-lite specification, Spec Section 3.6.1, "during a waited transfer, the master is permitted to change the transfer from IDLE to NONSEQ".
There are no definition for HRESP response for the above section.

What HRESP response can master change the transfer from IDLE to NONSEQ? Is it OK to change the transfer from IDLE to NONSEQ even if HRESP is NON-OKAY, -i.e.- ERROR case?

Best Regards,
-- Tsuneyoshi Yakabe
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#2 User is offline   JD 

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Posted 09 May 2012 - 09:10 AM

The HRESP value driven during the IDLE to NONSEQ change would be the response to whatever was driven on HTRANS in the transfer BEFORE the IDLE.

AHB transfers work in 2 phases, the address phase where HTRANS is signalled for the transfer, and then the data phase when the selected slave responds with HRESP.

So while the master is changing HTRANS from IDLE to NONSEQ, the data phase response being returned will relate to the previous address phase, not the current address phase.

If the HRESP being returned is a SPLIT or RETRY, this forces the master to change the CURRENT address phase to an IDLE, so that would stop the IDLE-NONSEQ transition, but that is not really what you were asking B)

JD
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