[Erico]

Hi members!
I consider integrating AXI-4 Bus in one of our SopC designs.
The AXI-4 Bus is intended to replace an existing non-standard Bus connecting several Masters to a DDR Memory Interface.
Along with traditional Burst Accesses, my actual design also supports Random Access cycles, in which the accessed address
may change on every clock during the cycle burst phase, and not only on the cycle starting phase, like for a regular Burst,
in which the access occurs to successive addresses only.
Can AXI-4 Bus support such cycles ?
Thank's

[JD]

The AXI protocol requires that you indicate how long a burst will be, you supply a start address, and you must then perform that number of transfers.

If you want to access lots of "random" addresses, where you are not then performing a burst of sequential accesses, you will just need to signal lots of AXI bursts of length 1 transfer, and that way you can supply a new address for each transfer.

JD