[lsjk]

Hi experts,

On cortex-a9, does TTBR RGN,S bits need to match those in page table entry ?
For example, if I set TTBR RGN bits = WBWA (inner and outter write back write allocate) to let
TLB walk happen in cache, and set the memory that contains page tables
to TEX,C,B = 0,0,0 (strongly ordered). Will this work ? Or the memory contains page tables must also be set to WBWA ? Thanks.

[ttfn]

Yes and no.
Those settings are used when the processor does a table walk. If you the settings don't match the appropriate table entries, there is a risk of coherency problems.
Typically you either match the settings, or set RGN bits to uncached and do a cache clean after table modifications.

[lsjk]

引用框（ttfn ＠ 07 April 2012 - 12:55 PM）

Yes and no.
Those settings are used when the processor does a table walk. If you the settings don't match the appropriate table entries, there is a risk of coherency problems.
Typically you either match the settings, or set RGN bits to uncached and do a cache clean after table modifications.

I understand. But consider this: what if I configure ttbr to inner and outter WBWA, but page table to strongly-order, will this work ? For what I understand, the memory that contains page table will never be brought into cache because I put page tables into strongly ordered memory, and when tlb walk happens, it will cause a cache miss and fetch data from external memory. So in this case the tlb walk and CPU also see consistent data, only this time the memory access will be slower ? I am asking because I see a little bit faster tlb walk than other configurations which is weird because SO memory is supposed to be very slow.