Cortex-A9 MPCore Fastmodel Trustzone support
Posted 21 March 2012 - 09:18 AM
Posted 27 March 2012 - 08:09 AM
However, in terms of interrupts there is nothing too special about it. It uses the A9's in-built interrupt controller. We have a mix of secure (FIQs) and non-secure interrupts (IRQs) being generated, not seen any problems.
Posted 27 March 2012 - 11:54 AM
Posted 27 March 2012 - 11:59 AM
If I use the example projects, I am not getting any group1 interrupts i.e. non-secure interrupts. Even writing to GIC Distributor control register enables only secure interrupts. If I try to write 0x3 in GIC distributor control register, it got set with 0x1. But if I try the same in Cortex A8 example project, I am able to enable both non-secure and secure interrupts. But in Cortex A8, FIQ interrupts are not working.
It is kind of trick situation and I don't know about the hardware modelling.
Posted 27 March 2012 - 09:22 PM
As far as the interrupt controller is concerned there is no such thing as a secure interrupt, other than non-secure software cannot configure a secure interrupt or set high priority. The interrupt handling is entirely a software problem in the ARM core, and not really very much to do with the GIC at all.
By "not seeing any non-secure interrupt" it sounds like you think the interrupts are being generated but they are not appearing in the normal world interrupt handler?
Ensure that you have correctly configured hardware trapping to the monitor mode for interrupts in CP15, and that your monitor software is context switching cleanly when the interrupt occurs.
See section 3.3 of http://infocenter.ar...492c/index.html for an intro.
Posted 28 March 2012 - 04:25 AM
I have configured all the GIC interrupts as group 1 interrupts in secure application and switched to non-secure mode by setting the secure configuration register and I followed the other steps like configuring the GIC priority, CPU registers and also configuration related to SCU. After that I try to load the linux or baremetal application. But in linux it got stuck in "calibration timer" and it is because it doesn't receive timer interrupts. I seen the similar issue with baremetal non-secure application. I am using the A9MPCore fast model example project supplied by ARM. On debugging the issue, in the model debugger, GIC distributor control register is not banked. I can see only one register in case of GIC distributor control register. In case of GIC CPU control register, it has 2 sets of registers. One is for non-secure and other one for secure mode.
I am sure that I am missing the configuration or connection in the A9fast model project. As I am not familiar with ARM fast model customization, I posted the question to see whether any one able to use the default example project.
Thanks a lot for all valuable comments.
Posted 28 March 2012 - 08:02 AM
Setting this bit in the register does not force the interrupt to switch to non-secure, it forces the interrupt to switch to monitor mode. Your monitor mode software is responsible for context switching safely to the right world.
Can you connect a debugger and set some breakpoints on the secure and monitor mode vector tables? That would at least prove the interrupt is being generated and trapped correctly.
Posted 28 March 2012 - 08:25 AM