[Zijay]

Hi all,

Recently, I'm studying AXI4 ACE spec. and working on ACE design,
but getting confused about the usage of shareability domain.

As per ACE spec.
"A shareability domain is a set of master components that enables a master component
to determine which other master components to include when issuing coherency
or barrier transactions."

Some questions:
1) A master component issues a coherent trans on an address region, it must set AxDOMAIN
as suitable domain (Inner/Outer/System), how to determine the address or access region of a AXI trans
belongs to which shareability domain ?

2) When the interconnect component (ex: CCI400) receives a coherent trans from ACE master,
it read the AxDOMAIN to determine which masters need to issue snoop trans,
but how to interpret the AxDOMAIN mapped to which masters ?
The relations of mapping Inner/Outer/System domains to a set of masters should be determined
in design time, such as memory map of all slaves connected to interconnect module ?

Above are my understanding and questions,
if anything wrong, please correct me, thanks.