[something]

Dear All,Now I am reading the ARM_ARM . At P1265, Secure and Non-secure address spaces,it says
"When implemented, the Security Extensions provide two physical address spaces, a secure physical address space and a non-secure physical address space."

But I can not realize the mean of it.
As we know,Secure Extension provides the banked TTBR0, TTBR1 and TTBCR to let us have two virtual address spaces.
But why it says two physical address spaces?

Thank you.

[ttfn]

The "two physical address spaces" thing can be quite confusing. The first thing to get straight is the theory VS how its typically used.

ARM's architecture defines two physical address spaces: secure (s) and non-secure (NS). Architecturally NS:0x8000 is a completely different and independent location to S:0x8000.

This is how the processors work. So if generated accesses to NS:0x8000 and S:0x8000 you could end up with both locations in the cache at the same time. The caches would treat them as being different locations.

If you were to look at the bus, you would see the processor put out 0x8000 for both locations . A separate signal (called AxPROT if you're interested) is used to tell the memory system whether its NS:0x8000 or S:0x8000 that the processor wants to access.

In theory this means that a chip could have two complete physical address spaces S and NS. In practise my experience is that this rare! Most the of the chips I have worked with use NS vs S as primarily a form of access control. So you might have a memory at address 0x8000, and it should be secure accessible only. Then any access to S:0x8000 will succeed, and any access to NS:0x8000 would generate a bus fault (abort exception).

[something]

ttfn, on 17 November 2011 - 06:04 PM, said:

If you were to look at the bus, you would see the processor put out 0x8000 for both locations . A separate signal (called AxPROT if you're interested) is used to tell the memory system whether its NS:0x8000 or S:0x8000 that the processor wants to access.
In theory this means that a chip could have two complete physical address spaces S and NS. In practise my experience is that this rare! Most the of the chips I have worked with use NS vs S as primarily a form of access control. So you might have a memory at address 0x8000, and it should be secure accessible only. Then any access to S:0x8000 will succeed, and any access to NS:0x8000 would generate a bus fault (abort exception).

Thank you very much for your brilliant explain,especially the last paragraph.
I think your mean is the ARM Security Extensions support two physical address spaces by providing the a separate signal (AxPROT) to let the memory controller can distinguish the secure memory access and the non-secure memory access, but there is a complicated memory controller must be designed to match up it.
So in practice most memory controller is only designed to prohibit the accessing secure memory from non-secure world. (actually it is the way my company doing)
If the simply scheme is selected, the physical address space is same between secure world and non-secure world.

I don't know if I comprehend your mean correctly.
Thank you very much once again.

[ttfn]

Yes, you seem to have got it

What you may also find is some peripherals use the AxPROT signal - again as access control. Non-secure accesses can configure a sub-set of the functionality, while secure accesses can configure everything. An example of this is the GIC-390 interrupt controller.