[WildClyde]

When was the vldx.64 instuction (where x can be 1, 2, 3, or 4) added and is it in all Neon implementations?

The ARM DDI 0406B ARM Architecture Reference Manual ARM v7-a and ARM v7-R edition does not document the vldx.64 instruction (see page A8-604). This is very frustrating to someone trying to learn the instruction set. Sizes of .8, .16, and .32 are documented.

When .64 is specified, does the memory argument have to be on a memory address evenly divisible by 8?

Thanks!

[sim]

WildClyde,

Only some variants of VLD1/2/3/4 support the use of 64 bit elements, the one you refer to doesn't.
In this particular case it wouldn't make sense as a 64-bit single-lane-load into a D or Q would be equivalent to a simple 64-bit load into a D.
It may be that some assembler will except the first and generate the second.

hth
s.

[WildClyde]

The code that I am trying to trouble shoot is code contained in the FFMPEG X264 library:

vld1.64 {d0-d3}, [r1,:128]

I am trying to figure out if the issue is that the Snapdragon QSD8650 does not support this vld varient or if the issue is that the pointer in r1 is not aligned on an 8 byte address boundry (evenly divisible by 8). Other Neon instructions are supported correctly.

Thanks.

[Exophase]

64-bit vld is only supported for vld1 with multiple single elements. You can see it A8-603 of DDI 406B. I'm sure your processor supports it, but without knowing more about what's going wrong for you there's not much anyone can say to help you.

The .64 will require that the address is 8-byte aligned only if SCTLR.A is 1, which I would assume your OS wouldn't do. But the ,:128 requires it to be aligned by 16 bytes, so the entire question is moot.

[WildClyde]

Thanks Exophase!