[NDW]

Hi Everyone,

I am a computer science major beginning work on a Capstone Project. I have been given the task of simulating an Arm Processor. I'm fairly new to this area of study, and am still learning but I'm very excited for the project.

In my early attempts at grasping the architecture I've run into a small roadblock. As i work my way through the Arm reference manual I've found myself somewhat unclear on the manner in which Addressing modes are indicated. From what I gather this occurs through use of the 'I' bit (bit 25 of the word), and bits 4 and 7 of the shifter operand.

I understand that the instructions are encoded, and using sections 3.1, 4.all and 5.2 I'm starting to put this stuff together.

What I'm curious about is if someone has some simple examples or a more clear explanation of the process they could share with me. The reference manual is great, but its dense and i could use another viewpoint.

Also - first post, its awesome that these forums are here.

Thanks,

NDW.

[NDW]

To Give an example:

I'm looking at the ADD command.

#<immediate>

The oppcode (bits 27,21) of this command would be - 0010100 - or 0x14

In this case bits 7 and 4 are not involved in determining the addressing mode as the I bit is not 0?

<Rm>

The oppcode (bits 27,21) of this command would be 0000100 or 0x4

with 7 and 4 being set to 0...

In this case were 7 and 4 to be set to 1 it would be an extended instruction?

Just trying to give an example of what my understanding is. Thanks folks.

[scott]

You don't say what version of the ARM ARM (ARM architecture refence manual) you are using, but revision I seems close.

引用框（NDW ＠ 27 September 2011 - 03:16 PM）

To Give an example:

I'm looking at the ADD command.

#<immediate>

The oppcode (bits 27,21) of this command would be - 0010100 - or 0x14

In this case bits 7 and 4 are not involved in determining the addressing mode as the I bit is not 0?

"Addressing mode" is a strange way to descibe it since the data processing instructions like ADD cannot access memory. I take it you're trying to figure out how to distinguish between different forms of ADD, for example "ADD Rd, Rn, #imm" and "ADD Rd, Rn, Rm". Table A3-1 and it's footnotes are your friends.

The "ADD Rd, Rn, #imm" case is the "Data processing immediate" line (6th) of Table A3-1. Bits 7 and 4 of the instruction are both part of the immediate field.

引用框（NDW ＠ 27 September 2011 - 03:16 PM）

<Rm>

The oppcode (bits 27,21) of this command would be 0000100 or 0x4

with 7 and 4 being set to 0...

Now you're talking about the "Data processing immediate shift" line (1st). Bit 4 of the instruction must be zero and bit 7 is part of the shift_amount field.

引用框（NDW ＠ 27 September 2011 - 03:16 PM）

In this case were 7 and 4 to be set to 1 it would be an extended instruction?

If bit 4 is not 0 then it's a different line of the table (and is a different instruction). The line that applies when bits 7 and 4 are both 1 is the "Multiplies and xtra load/stores".line (5th).