[GaneshK]

I want to know about efficient data passing techniques to AMBA peripherals in a Cortex M1 system.

The memory is accessed 32 bits but I know of no other way, than using AMBA protocol signals(single register read/write). My hardware peripheral has registers and offsets which are memory mapped in processor space.
Can I make my C program use memory mapped peripheral as storage locations?
What happens if I do as below?



int * x; // What if I make it volatile int ?
x=0x1234567 //Actual Address of AHB or APB peripheral.


So if I do x[]={10,20,30,40} can all these 4 values be written to my peripheral where I declare Reg A,B,C and D with offsets of 4 bytes between them?
Also if it does happen what would be the sequence of hardware signals??


Any replies specific to Cortex M1 would be very much helpful.

This post has been edited by GaneshK: 14 August 2011 - 04:45 PM

[sim]

An address ending in 0x..7 wouldn't work on M0 or M1 as it has to be a multiple of 4 bytes to support a 32-bit access.

A typicaly method for accessing AHB devices on M1 from C is to define a struct of volatile members, e.g.:

typedef struct mydevice_s {
  volatile int RegA; // offset 0x0
  volatile int RegB; // offset 0x4
  volatile int RegC; // offset 0x8
  volatile int RegD; // offset 0xC
} mydevice_t;

mydevice_t *DevA = (mydevice_t *)0xA0000000;

int main(void)
{
  DevA->RegA = 10;
  DevA->RegB = 20;
  DevA->RegC = 30;
  DevA->RegD = 40;
  return 0;
}

The use of volatile informs the compiler that it should not optimise out, or re-order accesses to these objects.

The resulting AHB traffic will look something like:

# HADDR  | .. | 0xA0..00 | .. | .. | 0xA..4 | .. | .. | 0xA..8 | .. | .. | 0xA..C | .. |
# HTRANS | .. | 2 (NSEQ) | .. | .. |   2    | .. | .. |   2    | .. | .. |   2    | .. |
# HSIZE  | .. | 2 (WORD) | .. | .. |   2    | .. | .. |   2    | .. | .. |   2    | .. |
# HWDATA | .. | ........ | 10 | .. | ...... | 20 | .. | ...... | 30 | .. | ...... | 40 |

AHB would permit them to be issued as follows, though this is dependent on the capabilities of the master:

# HADDR  | .. | 0xA0..00 | 0xA..4 | 0xA..8 | 0xA..C | .. |
# HTRANS | .. | 2 (NSEQ) |   2/3  |   2/3  |   2/3  | .. |
# HSIZE  | .. | 2 (WORD) |   2    |   2    |   2    | .. |
# HWDATA | .. | ........ |   10   |   20   |   30   | 40 |

hth
s.