[Jerry Fan]

I changed CPSR to 0x1D0(which means USR mode )in SVC mode in cortex-a8 platform(freescale imx51), but a perfetch_error occured, the PC hung at 0x0c. Could anybody help me figure this issue out, please?
OR anybody has some code some hwo to enter USR mode from SVC mode?

Best Regards
Jerry

[Christophe31]

Hi Jerry,

Here is how I do for Cortex-R4F :

mrs r1, cpsr
orr r1, r1, #0x0010
bic r1, r1, #0x000F
msr cpsr_c, r1

Hope it helps

Best regards

Christophe

[Jerry Fan]

引用框（Christophe31 ＠ 01 August 2011 - 08:13 AM）

Hi Jerry,

Here is how I do for Cortex-R4F :

mrs r1, cpsr
orr r1, r1, #0x0010
bic r1, r1, #0x000F
msr cpsr_c, r1

Hope it helps

Best regards

Christophe

Thank, Chris
I tried the code on Cortex-a8(freescale i.mx51), it does not work. Once "msr cpsr_c, r1" , a undefined instruction exception occured.

BR
Jerry

[Christophe31]

Hi Jerry,

Hum, it is strange, because Cortex-A8 and R4 seem to share the same architecture !? What is your compiler ? (for me, it works with both RVCT 4.0 and CCS v4)

did you also try
msr cpsr, r1
?

cpsr_c is a sub mask for writing only specific bits... maybe not available for cortex-A8

Regards

Christophe

This post has been edited by Christophe31: 02 August 2011 - 09:13 AM