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ARM Community: Region signals in AXI4 - ARM Community

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Region signals in AXI4 Rate Topic: -----

#1 User is offline   sreenath 

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Posted 28 July 2011 - 05:36 AM

Hi,
We have new signals being added in AXI4:

- AxREGION

If we look into the spec, it indicates - "it must only be present on an interface that is downstream of an address decode function".

Also spec does state that - "Typically Interconnect drives these signals".

So does it mean they are redundant from Master perspective? Master can driven them to any value and then Interconnect can take action on driving correct region value?

Please clarify.

Thanks
-Sreenath
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#2 User is offline   JD 

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Posted 28 July 2011 - 09:31 AM

It is unlikely that an interconnect could use AxREGION indications from a master, and it is unlikely that the master could sensibly signal anything on them (the master doesn't usually know the physical structure of the slaves in the system, so wouldn't have the knowledge to signal meaningful region numbers), so I wouldn't expect to see AxREGION outputs on any master.

And as the AxREGION signals are optional, it doesn't make any sense in driving a default value on them from your master.

The interconnect is implementing a specific address map, and should be aware of all the slaves it is connecting to, so it can sensibly use region numbers where appropriate for that slave.

JD
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#3 User is offline   sreenath 

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Posted 28 July 2011 - 09:56 AM

View PostJD, on 28 July 2011 - 09:31 AM, said:

It is unlikely that an interconnect could use AxREGION indications from a master, and it is unlikely that the master could sensibly signal anything on them (the master doesn't usually know the physical structure of the slaves in the system, so wouldn't have the knowledge to signal meaningful region numbers), so I wouldn't expect to see AxREGION outputs on any master.

And as the AxREGION signals are optional, it doesn't make any sense in driving a default value on them from your master.

The interconnect is implementing a specific address map, and should be aware of all the slaves it is connecting to, so it can sensibly use region numbers where appropriate for that slave.

JD


Thanks JD, it matches with my interpretation.

-Sreenath
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#4 User is offline   Phani Emani 

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Posted 28 July 2011 - 05:04 PM

Hi,

I am new to this forum. I am also looking for clarification on AxREGION signal.

This is bit confusing for me.

1. Spec says that this signal is driven by Master.

2. Assume a simple interconnect with two Masters M1 and M2 on one side and Slave S on other side. Say the application side of Master M1 is PCI-E. The VC(VirtualChannel) number can be directly driven onto the REGION signal, along with address etc., In this case, Master M1 can implement MxREGION right? The interconnect will just pass the REGION to slave.
As you clarified, the other Master M2 may not implement REGION and interconnect will need to drive this signal.

--Phani.
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#5 User is offline   JD 

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Posted 01 August 2011 - 09:02 AM

Phani,

The spec does say that the AxREGION signals are driven by a master, but further qualifies this with "AxREGION must only be present on an interface that is downstream of an address decode function".

Remember that in AXI a "master" can be the port on an interconnect that connects to a slave, so that is the sort of "master" you would typically see AxREGION used on. Actual AXI processor cores would probably not include any decode function that could sensibly indicate a region number going in to an interconnect "slave" port.

In your application, if the PCI-E Virtual Channel number is based on an address decode function, and this number if then specific to part of a single final-destination slave, you could legitimately use it to drive the AxREGION signals.

However I would still expect to see most AXI interconnect designs ignore any possible region indicator from the connected masters, and instead just issue AxREGION numbers based on the interconnects own address decode function, so whether it is worth using your PCI-E VC number to drive AxREGION outputs from your AXI master would depend on your interconnect design.

JD
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