We have integrated Coresight in our Cortex A9 based SOC.
Using Coright DK-A9 Integration Design Kit we are bringing up the testbench for integration testing.
In parallel I want to test the integration through JTAG DP (we use APB MEM-AP) in simulation using my existing Design Verification Environment.
Has anyone tried this and can share the Jtag sequences to issue for this purpose. What sequences to issue and what to expect to confirm that the Coresight has been integrated correctly.
I would be using DAP Macro Language for this purpose. Our environment has ARM DSM and not the actual RTL.
Appreciate your help.
This post has been edited by RajatAsic: 23 February 2011 - 06:58 AM