[devendra]

we are working on a project to implement swjtag debugger for cortex boards. we had the reference manuals for cortex swdp, core sight, etc available at infocenter.arm.com

we are trying it accordingly. we were able to generate the switching sequences, packets etc properly as per the information we have but we couldn't get any acknowledgment packets from the processor. we are sure that we are missing some timing/other details . we will be thankful if you can help us in getting the complete timing sequence from power-on of the processor to ID code read in SWDP mode.that means to change the processor mode to swdp mode and requesting ID CODE read..

we are using our own compiled version of openocd software as debug software, we are generated the sequences using this software and verified this sequence from FT2232H to cortex processor using logic analyzer. We are generating the sequences perfectly as given in the reference manual of cortex.

[Joseph Yiu]

Which microcontroller are you using?
For most Cortex-M3 device the SWJ-DP is used (support both JTAG and SWD protocol).
By default it is in JTAG mode, and you need to use a sequence to switch it to SWD mode.

See http://infocenter.arm.com/help/topic/com.a...c.html#Chdgdijb

If you are using Cortex-M0 devices with Serial-Wire debug, you do not need this sequence.

Full details of the Serial-Wire protocol is documented in ARM Debug Interface Architecture Specification
http://infocenter.arm.com/help/topic/com.a...031a/index.html

You can also find some timing diagrams in CoreSight component TRM.
http://infocenter.arm.com/help/topic/com.a...h/Babcfacj.html

[devendra]

thanks for your reply Joseph..

We have used cortex-M3 from Luminary Micro(LM3S6965), We sent the sequences given in the Core-sight trm ,

The sequence order we sent to the processor:

1. 56 number of 1's on SWDIOTMS.(i.e more than 50 clk cycles)
2. The 16 bit sequence given by the ARM trm
3. 56 number of 1's on SWDIOTMS.

with this we can assume it changed to SWD mode

we sent the data to perform IDCODE register read.. that sequences are

1. one time we have sent 0 to indicate the start of the packet request ( because the start bit ='1')/ one time we directly sent the ID CODE register read request


2. the command for this operation : 1 1 1 0 0 0 0 1

start=1, (1 bit MSB)
ID CODE register is AP APnDP bit =1(2nd bit)
RnW bit=1 for read operation(3rd bit)
A[2:3]=00 for ID CODE(4,5 bits)
Parity bit=0 (6th bit)
stop bit=0 (7th bit)
park bit= 1 (8th bit)

by sending this command sequence , after 1 Trn clock cycle I tried to read the acknowledge ( the data from the processor i .e next 3 bits..) i got all 1's..

this is not in the possible acknowledgment..

Can anybody help with this issue..??

This post has been edited by devendra: 24 April 2010 - 05:05 AM

[CeDeROM]

Hello!

I am creating Open Source SWD library http://libswd.sf.net that will be incorporated into UrJTAG and OpenOCD.. and had exactly the same issue that comes from incompetent messy documentation (nightmare!!) provided by ARM.

1. IDCODE register is on DP, therefore APnDP should be 0, not 1 as stated in documentation.
2. After RESET, JTAG-TO-SWD, RESET you need additional IDLE sequence (SWDIOTMS=0 + 8 pulses on SWCLK) before REQUEST, otherwise target won't respond. There is no even half word on this in the jtag-to-swd section of the documentation!
3. Remember that ACK and DATA are clocked out LSBfirst not MSBfirst as displayed on the documentation, which is confusing.

I got this working using FT2232H chip working with highest possible speed :-)

Best regads,
Tomek Cedro

[Cortex fan]

Tomek:

I looked at your code on sourceforge.net and noticed you had created an Open SWD project for Cortex ARMs. Do you have the correct configuration settings for UrJtag (using a JTAG interface) for a Cortex M0 processor? Can you post the required UrJTAG/data files? Thanks )