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Cache Invalidation in Cortex-A8
#1
Posted 02 April 2010 - 11:33 PM
I am working on Cortex-A8 for my Application development.
Since OS I am using does not support MMU, I have created page table and configured MMU. I have configured the entire DDR as Cacheable (Write Through). The other region in the Memory space is defined as Non-cacheable.
For Invalidation I have followed Set / Way Method. The Other is MVA (Modified Virtual Address, I am not aware of Using it).
My Application has many DMA operations. So whenever a DMA occurs, I need to Invalidate the Cache. I am invalidating the entire Cache by Set/Way method.
But the invalidation of the entire cache consumes around 800uS, which can no where be compromised in my Application. Bcoz DMA may occur for even 32KB. But I will be invalidating the entire Cache; so eventually I will loose the Data in Cache and needs refiling again.
Im invalidating the Entire Cache, Since I don't know which Cache line (Block) would have been updated with this particular address (filled by DMA Data).
Is MVA a better process that I can follow to Invalidate the cache?? How can I use it to invalidate the Cache at a particular Address??
#2
Posted 03 April 2010 - 01:21 AM
TAK2064, on Apr 3 2010, 08:33 AM, said:
I am working on Cortex-A8 for my Application development.
Since OS I am using does not support MMU, I have created page table and configured MMU. I have configured the entire DDR as Cacheable (Write Through). The other region in the Memory space is defined as Non-cacheable.
For Invalidation I have followed Set / Way Method. The Other is MVA (Modified Virtual Address, I am not aware of Using it).
My Application has many DMA operations. So whenever a DMA occurs, I need to Invalidate the Cache. I am invalidating the entire Cache by Set/Way method.
But the invalidation of the entire cache consumes around 800uS, which can no where be compromised in my Application. Bcoz DMA may occur for even 32KB. But I will be invalidating the entire Cache; so eventually I will loose the Data in Cache and needs refiling again.
Im invalidating the Entire Cache, Since I don't know which Cache line (Block) would have been updated with this particular address (filled by DMA Data).
Is MVA a better process that I can follow to Invalidate the cache?? How can I use it to invalidate the Cache at a particular Address??
I don't know well OS.
If you want us DMA, you have to Non-cacheable area for DMA.
At the Linux, you could refer the dma-mapping.c (arch/arm/mm/dma-mapping.c)
#3
Posted 03 April 2010 - 04:35 PM
zerojin, on Apr 3 2010, 01:21 AM, said:
If you want us DMA, you have to Non-cacheable area for DMA.
At the Linux, you could refer the dma-mapping.c (arch/arm/mm/dma-mapping.c)
Hi Zerojin,
Currently, I have tried with MVA invalidation to invalidate the Blocks after DMA.
But even this eventually adds up a delay.
Thanks for the Input. I will try the same at my end.
#4
Posted 05 April 2010 - 01:47 PM
TAK2064, on Apr 3 2010, 06:03 AM, said:
I am working on Cortex-A8 for my Application development.
Since OS I am using does not support MMU, I have created page table and configured MMU. I have configured the entire DDR as Cacheable (Write Through). The other region in the Memory space is defined as Non-cacheable.
For Invalidation I have followed Set / Way Method. The Other is MVA (Modified Virtual Address, I am not aware of Using it).
My Application has many DMA operations. So whenever a DMA occurs, I need to Invalidate the Cache. I am invalidating the entire Cache by Set/Way method.
But the invalidation of the entire cache consumes around 800uS, which can no where be compromised in my Application. Bcoz DMA may occur for even 32KB. But I will be invalidating the entire Cache; so eventually I will loose the Data in Cache and needs refiling again.
Im invalidating the Entire Cache, Since I don't know which Cache line (Block) would have been updated with this particular address (filled by DMA Data).
Is MVA a better process that I can follow to Invalidate the cache?? How can I use it to invalidate the Cache at a particular Address??
Hi,
I'm also working with CortexA8. I have a problem in enabling MMU. I don't know how to create Page table and configure MMU. Can you just tell me how you have created Page Table and configured MMU.
Thanks & Regards,
M.Raghavendra.














