[jenyam]

Hi all

Can Anybody tell me how to init IRQ and FIQ interrupts at cortex A9. According reference manual we can set secure interrupt to FIQ and non-secure to IRQ. The secure interrupt work excellent. The handle FIQ is executed. But with non-secure i have some problem. I see pending non-secure interrupt from GIC to CPU in pending register, but CPU not bring up IRQ handler.
Example:
"0" is secure interrupt. works ok
"1" and "32" non-secure interrupt

#define SOFTWARE_INT_ID 0x00
#define CPU_TARGET_LIST (0x03 << 16)
#define TargetListFilter (0x0 << 24)
#define SATT(id) ((id) << 15)
INTC_DISTR_SetDisableCorrespondingInt(0);
INTC_DISTR_SetDisableCorrespondingInt(1);
INTC_DISTR_SetPriority(0, 1);
INTC_DISTR_SetPriority(1, 0x0);
INTC_DISTR_SetPriority(32, 0x0);
INTC_DISTR_SetSecurityStatus(1);
INTC_DISTR_SetSecurityStatus(32);
INTC_DISTR_SetIntProcessorTarget(1+31, 1);
INTC_DISTR_SetEnabeCorrespondingInt(0);
INTC_DISTR_SetEnabeCorrespondingInt(1);
INTC_DISTR_SetEnabeCorrespondingInt(1+31);
INTC_CPU_SetInterruptPriorityFilter(0xf0);
INTC_CPU_EnableSignallingOfInterrupts();
INTC_DISTR_SetForwardsPendingToCPU();
MxSetARMIntCtrl(INT_CTRL_IRQ_ENABLED | INT_CTRL_FIQ_ENABLED); //clear I and F
Distr->SoftGenInt = SOFTWARE_INT_ID | CPU_TARGET_LIST | (TargetListFilter) | SATT(0);
INTC_DISTR_SetPendingInt(32);
Distr->SoftGenInt = (SOFTWARE_INT_ID + 1) | CPU_TARGET_LIST | (TargetListFilter) | SATT(1);

Thanks

This post has been edited by jenyam: 20 November 2009 - 01:15 PM

[isogen74]

By non-secure interrupts I assume you mean configured as non-secure in the GIC configuration.

How is the CP15 Secure Configuration Register configured to route interrupts - if CP15 is configured to route interrupts to the "Non-secure" world, then you will have to have set up an appropriate piece of monitor mode code to perform the world switch (so control can be passed to the non-secure interrupt handler). That said - a non-secure GIC interrupt can still be routed to the secure world in the CPU - the CPU and the GIC are programmed separately.

There is a good guide to TrustZone interrupt handling in the ARM document library:

http://infocenter.arm.com/help/topic/com.a...492c/index.html

[jenyam]

I am using GIC in Cortex A9MP and want to use both IRQ and FIQ handler for diferent interrupts. To select the handler I am going to set corresponding bits in Interrupt Security Registers (ICDISR), but I am going to use only secure world. Will it work?
I expect to catch non-secure interrupt by interrupt handler in secure world, but I can't do it. I see that Highest Pending Interrupt Register (ICCHPIR) doesn't get ID of non-secure interrupt, despite non-secure interrupts are enabled in CPU Interface Control Register (ICCICR) and interrupt has pending status in the distributor. Has anybody done something similar?

This post has been edited by jenyam: 20 November 2009 - 01:14 PM

[Vaibhav Malik]

Hi

I find this relevant to my problem. I am also trying to configure GIC for my system. From the background, the system has legacy interrupt controller which is deployed in the new system with Cortex-A9 MPCore (x1).

[ Legacy Interrupt Controller ] --> [ GIC { Distributor --> CPU Interface} ] --> Processor

If I use GIC in the default configuration where both the distributor and cpu interface is kept as disabled (i.e bypass mode), I am able to see the nIRQ and nFIQ as legacy interrupts are passed successfully to the CPU and the corresponding interrupt handlers get executed successfully.

I tried configuring GIC distributor with the following sequence

[1] Disable the whole controller by disabling the distributor
[2] Clear all the pending interrupts with distributor by writing 0xffff_ffff
[3] Enable all the interrupts
[4] Reset the priority for all the interrupts by writing 0x0000_0000
[5] Interrupt targets are silent for write as CortexA9 MPCore has only one processor (as per specs)
[6] Enabling the distributor

Then I follow the following sequence to configure GIC CPU interface

[7] CPU configuration 0 & 1 for PPI, SPI and SGI level/edge sensitive
[8] Disable the CPU interface
[9] Set the higher priority as 0x1f with PRM register
[10] Enable the CPU Interface

I do this configuration in the firmware when I am sure that there is no possibility of an interrupt in the system and when the system reaches to the area where interrupt is expected, legacy interrupt controller generates an interrupt to the distributor. I can confirm from the pending interrupt register of the distributor and from the PPI status register as well. The pending status of the interrupt against ID31 is set to 1 (as per specification this is when CPU interface is not in bypass mode for legacy interrupts). The problem I am having is that the corresponding interrupt handler in the system for IRQ and FIQ never get control i.e. interrupt remains pending on the distributor, I believe.

Is there anything I have missed from the initial setup? Is there any way we can say whether the interrupt has been forwarded from the distributor to the CPU interface i.e. whether it is within distributor or CPU interface boundary?

Thanks in advance,

Vaibhav

This post has been edited by Vaibhav Malik: 10 September 2012 - 07:29 AM