[DivyaM]

Hi Everyone,
If i run the same code in both AXD and RVDS 3.0 (Target is ARM Simulator) will there be any difference between Corecycles of AXD and RVD?


Thanx in Advance

This post has been edited by DivyaM: 31 March 2008 - 05:57 AM

[Rich C]

Hi,

ARMulator in ADS/AXD is now called RVISS in RVDS, so I wouldn't expect any difference. RVISS = RealView Instruction Set Simulator.

Cheers,
Rich

[DivyaM]

Rich C, on Apr 1 2008, 02:20 PM, said:

Hi,

ARMulator in ADS/AXD is now called RVISS in RVDS, so I wouldn't expect any difference. RVISS = RealView Instruction Set Simulator.

Cheers,
Rich

Hi..
I have taken a sample application which initializes the value of variable and prints that variable. like

int main()
{
int i = 10;
printf("i = %d\n",i);
return 0;
}

When i run this code in AXD (ARM946E-S Processor) i got 4588 cycles.
Same code when i run it in RVDS (ARM946E-S Processor, Local Host) i got 11497 Cycles.

Can anyone plz explain me why there is a differnce in the Cycle count?

regards
Divya

[isogen74]

printf is a system call, which by default talks to the debugger using semi-hosting. This is outside of the scope of the ARM core as the core is stopped while semihosting executes, and such calls can take a long time to complete; dependent on the model and debugger being used.

I'm not sure how the models count cycles when semi-hosting is used. In general only count cycles for genuine instructions (no talk to semihosted SWIs or virtual hardware) - anything using semi-hosting is liable to produce odd results.

[SoupDragon]

DivyaM, on Apr 4 2008, 01:17 AM, said:

When i run this code in AXD (ARM946E-S Processor) i got 4588 cycles.
Same code when i run it in RVDS (ARM946E-S Processor, Local Host) i got 11497 Cycles.

Can anyone plz explain me why there is a differnce in the Cycle count?

regards
Divya

I have a feeling that AXD/ARMulator configure caches as on by default while RVD/RVISS configures caches as off by default. Check the RVISS configuration and check the option 'Default pagetables' is turned on.

SD

[DivyaM]

-> In that Sample Program if i remove the printf statement and the initialization of Variable, with only return statement in main().. still the cycle count is not same ie. AXD - 398 cycles and RVD - 998 cycles.

-> In both AXD/ARMulator and RVD Default Page tables is selected. So The cycle count is differed not because of Default Pagetables.

I am new to RVD. I have the problem on deciding whether the Performance is to be calculated based on Core cycles of AXD or RVD.?

Plz help me on this..

Regards
Divya

[SoupDragon]

DivyaM, on Apr 7 2008, 02:20 AM, said:

-> In that Sample Program if i remove the printf statement and the initialization of Variable, with only return statement in main().. still the cycle count is not same ie. AXD - 398 cycles and RVD - 998 cycles.

Interesting; the difference is approx. a factor of 3. Have you checked the MCFG option (which controls ratio of CPU to Bus cycles) is identical for both setups

Quote

I am new to RVD. I have the problem on deciding whether the Performance is to be calculated based on Core cycles of AXD or RVD.?

Does AppNote 93 help?

ARM Information Centre

Can you post the banners that are printed out by AXD and RVD when you connect to the simulator.

Regards
SD

[DivyaM]

SoupDragon, on Apr 8 2008, 02:21 AM, said:

Interesting; the difference is approx. a factor of 3. Have you checked the MCFG option (which controls ratio of CPU to Bus cycles) is identical for both setups



Does AppNote 93 help?

ARM Information Centre

Can you post the banners that are printed out by AXD and RVD when you connect to the simulator.

Regards
SD

I am attaching the cycles taken by both RVD and AXD for ARM920T Processor.

I dont know about MCFG option. Where is that option available and can u plz give me some information regarding this.

One more thing.. AXD uses the Default pagetables 2 (--dwarf2) where as RVDS uses the Defualt pagetables 3. So, will that make any difference ?


regards
divya

Attached File(s)

•  RVDebug_Cycles.JPG (78.46K)
  Number of downloads: 26
•  AXD_Cycle.JPG (14.91K)
  Number of downloads: 16

[SoupDragon]

DivyaM, on Apr 8 2008, 04:07 AM, said:

I am attaching the cycles taken by both RVD and AXD for ARM920T Processor.

Ok, but that's not much use yet...

Quote

I dont know about MCFG option. Where is that option available and can u plz give me some information regarding this.

This is mentioned in AN93, I think it's set to 3 in a config file default.ami

Quote

One more thing.. AXD uses the Default pagetables 2 (--dwarf2) where as RVDS uses the Defualt pagetables 3. So, will that make any difference ?

'Default pagetables' has nothing to do with debug data. DWARF 2 & 3 are formats for debug data in the image. Default pagetables is an RVISS/ARMulator option to control whether or not caches are enabled by default. If you have caches on in one simulation and off in another it would explain the difference.

Please post the banner printed in the console when you connect to the simulator for both RVD and AXD. It will look something like this...

> connect @localhost
> connect  @new_arm@localhost
ARMulator RVARMulatorISS1.4 [Build 297]
ARM926EJ-S, 16Kb I-cache, 16Kb D-cache, 64Kb I-Ram, 64KB D-Ram, 
Memory Management Unit, I-uTLB, D-uTLB, TLB, BIU, Little endian, 
Debug Comms Channel, 4GB, Mapfile, Timer, Profiler, SIMRDI MemCallback, Tube, 
Millisecond [6666.67 cycles_per_millisecond], IntCtrl, Tracer
Tracing: Instructions, Memory accesses, Events, Disassemble, Trace bus, 
Trace registers, Opcode Fetch
 Mask 0x00000000-0x00000000, RDI Codesequences, Semihosting

Regards
SD

[DivyaM]

ya.. i checked the MCCFG option. It is set to 3 in defualt.ami

RVDS BANNER


Workspace: Opening Connections...
Workspace: connect @new_arm@localhost:Server
ARMulator RVARMulatorISS1.4 [Build 297]
For support please contact support-arm@huins.com
Software supplied by: ARM Limited
ARM920T, 16KB I-cache, 16KB D-cache, (Physical memory, BIU), Little endian, 
Semihosting, Debug Comms Channel, 4GB, Pagetables, Mapfile, Timer, Profiler, 
SIMRDI MemCallback, Tube, Millisecond [6666.67 cycles_per_millisecond], IntCtrl, 
Tracer
Tracing: Instructions, Memory accesses, Events, Disassemble, Trace bus, 
Trace registers, Opcode Fetch
 Mask 0x00000000-0x00000000, RDI Codesequences, VFPv2 (no support code)
Workspace: Init/Open done.

AXD Banner

ARMulator RVARMulatorISS1.4 [Build 297]
For support please contact support-arm@huins.com
Software supplied by: ARM Limited
ARM920T, 16KB I-cache, 16KB D-cache, (Physical memory, BIU), Little endian, 
Semihosting, Debug Comms Channel, 4GB, Pagetables, Mapfile, Timer, Profiler, 
SIMRDI MemCallback, Tube, Millisecond [6666.67 cycles_per_millisecond], IntCtrl, 
Tracer
Tracing: Instructions, Memory accesses, Events, Disassemble, Trace bus, 
Trace registers, Opcode Fetch
 Mask 0x00000000-0x00000000, RDI Codesequences, SIMRDI VFP
ARM RDI 1.5.1 -> ASYNC RDI Protocol Converter RVDS v3.0 [Build number 132]. Copyright © ARM Limited 2001.

These are the Logs of AXD and RVDS.

Regards
Divya

[DivyaM]

DivyaM, on Apr 10 2008, 04:29 AM, said:

ya.. i checked the MCCFG option. It is set to 3 in defualt.ami

RVDS BANNER


Workspace: Opening Connections...
Workspace: connect @new_arm@localhost:Server
ARMulator RVARMulatorISS1.4 [Build 297]
For support please contact support-arm@huins.com
Software supplied by: ARM Limited
ARM920T, 16KB I-cache, 16KB D-cache, (Physical memory, BIU), Little endian, 
Semihosting, Debug Comms Channel, 4GB, Pagetables, Mapfile, Timer, Profiler, 
SIMRDI MemCallback, Tube, Millisecond [6666.67 cycles_per_millisecond], IntCtrl, 
Tracer
Tracing: Instructions, Memory accesses, Events, Disassemble, Trace bus, 
Trace registers, Opcode Fetch
 Mask 0x00000000-0x00000000, RDI Codesequences, VFPv2 (no support code)
Workspace: Init/Open done.

AXD Banner

ARMulator RVARMulatorISS1.4 [Build 297]
For support please contact support-arm@huins.com
Software supplied by: ARM Limited
ARM920T, 16KB I-cache, 16KB D-cache, (Physical memory, BIU), Little endian, 
Semihosting, Debug Comms Channel, 4GB, Pagetables, Mapfile, Timer, Profiler, 
SIMRDI MemCallback, Tube, Millisecond [6666.67 cycles_per_millisecond], IntCtrl, 
Tracer
Tracing: Instructions, Memory accesses, Events, Disassemble, Trace bus, 
Trace registers, Opcode Fetch
 Mask 0x00000000-0x00000000, RDI Codesequences, SIMRDI VFP
ARM RDI 1.5.1 -> ASYNC RDI Protocol Converter RVDS v3.0 [Build number 132]. Copyright © ARM Limited 2001.

These are the Logs of AXD and RVDS.

Regards
Divya

Can any one reply for this problem. It is very important for me...

thanx in advance
Divya

[mynameashishjain]

pagetable option will not affect the core cycle count.
whether you enable cache or not core cycle count will be same.
first thing you can try is to see the dissassembly of the code genarated and see how both the codes are different and which part is consuming more cycles.
second thing you can try is to use code which includes only basic instruction like add and mul then see the difference.

[DivyaM]

mynameashishjain, on Apr 15 2008, 09:24 AM, said:

pagetable option will not affect the core cycle count.
whether you enable cache or not core cycle count will be same.
first thing you can try is to see the dissassembly of the code genarated and see how both the codes are different and which part is consuming more cycles.
second thing you can try is to use code which includes only basic instruction like add and mul then see the difference.

int main()
{
   return 1;
}

I have Checked the Cycles for this code in RVDS and AXD. It doesnt have any printf's or arithmetic operations. But still the core cycles are different..

--> Before the control comes to return statement, there is difference in the cycles. Is the initialization code different for both AXD and RVDS?

thanx in Advance
Divya

[tomtsui]

Hi, I am encountering the same situation. Is there any reason why this would happen?

Thanks.

[Arruaba]

Does anyone know this problem now?

Plz help!

THX