http://forums.arm.com/index.php Tue, 18 Jun 2013 10:43:42 +0000 180 http://forums.arm.com/index.php?/topic/16859-emc-on-cortex-m3-lpc1788/ Dear All,
I am using LPC1788 (cortex M3) and have successfully interfaced SDRAM using EMC. Now i am trying to interface Nand Flash memory and implement Flash File system on it. As i dont have LPC1788 example code, i am referring to LPC2470 (ARM7) EMC code. I have connected Samsung IC - K9F1G08U0C (1Gbit Nand Flash).

The problem is that, when i read the status of the IC, it appears to be in ready state (R/!B line = 1). But when i execute fopen, it returns NULL. Cant figure out what is wrong?
Googled it. but didnt not come across any article, blog or even forum where this is discussed.
]]> Tue, 18 Jun 2013 10:43:42 +0000 http://forums.arm.com/index.php?/topic/16859-emc-on-cortex-m3-lpc1788/ http://forums.arm.com/index.php?/topic/16858-where-can-i-get-arm-verilog-code/ I have been working as a FPGA FAE for tens of years. Since ARM is such popular these years, as a personal insterest I am trying to port an ARM core into a FPGA. Can anyone tell me where can I get the synthesizalbe verilog code of ARM? Or I have to create the source code based on instruction set? Is it illegal? any comment will be appreciated. Tue, 18 Jun 2013 08:20:16 +0000 http://forums.arm.com/index.php?/topic/16858-where-can-i-get-arm-verilog-code/ http://forums.arm.com/index.php?/topic/16856-code-size-and-speed/
Keil uVision4 RealView compiler.

This Code is full of Variables of type "short" non of them need to be signed.

Would it reduce size and increase speed if i converted everything to "unsigned short" ??

From my 8051 days I would say def yes.]]> Fri, 14 Jun 2013 10:17:59 +0000 http://forums.arm.com/index.php?/topic/16856-code-size-and-speed/ http://forums.arm.com/index.php?/topic/16855-arm-thumb-behavior-on-cortex-a15/ Dear All
We are facing one issue in user space, if we enable thumb mode and in kernel
whether we enable or disable thumb mode or code run in both scenario.
we could not understand the reason.


Our core is ARM cortex A15,
Kernel 3.8.13
So I could not see any change CONFIG_ARM_THUMB.
If this is set or unset. my user space thumb compiled binary are running well.

arm-gcc-4.7.3 test.c -o test_thumb -mthumb

Thanks]]> Fri, 14 Jun 2013 05:52:33 +0000 http://forums.arm.com/index.php?/topic/16855-arm-thumb-behavior-on-cortex-a15/ http://forums.arm.com/index.php?/topic/16854-using-cmos10sf-cells-for-cmos10rfe-run/ The only available IBM 65nm cell library is CMOS10SF. So, I was wondering if it is possible to use CMOS10SF cells for CMOS10RFE run?

Thanks]]> Thu, 13 Jun 2013 14:25:18 +0000 http://forums.arm.com/index.php?/topic/16854-using-cmos10sf-cells-for-cmos10rfe-run/ http://forums.arm.com/index.php?/topic/16853-how-to-compile-sample-neon-code-on-windows/ I installed Real view development suite v4.1 professional in my windows PC.But i need to compile a simple NEON code.How to compile a codes in that.can u please reply me


Code is

#include <arm_neon.h>uint32x4_t double_elements(uint32x4_t input){ return(vaddq_u32(input, input));}]]> Thu, 13 Jun 2013 10:15:35 +0000 http://forums.arm.com/index.php?/topic/16853-how-to-compile-sample-neon-code-on-windows/ http://forums.arm.com/index.php?/topic/16852-running-linux-and-ucosii-in-amp-in-smp-mode-on-cortex-a9-mpcore-to-use-scu-for-cache-coherency/
i'm a Student and planning to implement Linux running on CPU0 and the uC/OSII for Real Time Response on CPU1 of the Cortex A9 MPCore in the Altera Cyclone V SoC.

Because i need to work with shared memory (guess that will be on the on chip RAM) i want to use the SCU to reach cache coherency without the need to implement it in software. Therefore the CPU's have to be configured in SMP Mode. So the question is if i can tell Linux only to run in CPU0 and boot uC/OSII on CPU1 in this Configuration ? To get rid of the impact from CPU0 to CPU1 throug cache acesses, i would disable the use of L2 Cache in CPU1.

Are there any other issue's about this "AMP" in "SMP" Mode i'm not thinking about?

Thanks,
Jenson]]> Thu, 13 Jun 2013 06:17:38 +0000 http://forums.arm.com/index.php?/topic/16852-running-linux-and-ucosii-in-amp-in-smp-mode-on-cortex-a9-mpcore-to-use-scu-for-cache-coherency/ http://forums.arm.com/index.php?/topic/16851-writing-to-the-system-control-register/ I am doing this in C. Any help will be greatly appreciated.]]> Wed, 12 Jun 2013 20:15:18 +0000 http://forums.arm.com/index.php?/topic/16851-writing-to-the-system-control-register/ http://forums.arm.com/index.php?/topic/16849-how-can-i-edit-elf-file/ Is there a way I can update existing .elf file.
I want to add couple of lines of code (few register writes), to existing elf code.
Is it possible to do so ?

Regards !!!]]> Wed, 12 Jun 2013 14:45:50 +0000 http://forums.arm.com/index.php?/topic/16849-how-can-i-edit-elf-file/ http://forums.arm.com/index.php?/topic/16848-barrier-instructions-while-enabling-and-disabling-interrutps/ I am using cortex A8/9 processors. I am not sure if i need to use barrier instructions before and after enabling/disabling instructions.
will not using them cause any unexpected behavior?

Can someone please clarify.

Regards
Baskaran]]> Wed, 12 Jun 2013 12:41:23 +0000 http://forums.arm.com/index.php?/topic/16848-barrier-instructions-while-enabling-and-disabling-interrutps/